
// Library name: VLSI_PROJECT
// Cell name: amk_inverter
// View name: schematic
subckt amk_inverter VDD VSS in out
    T1 (out in VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T0 (out in VSS VSS) lpnfet l=120.0n w=160.0n nf=1 m=1 par=1 ngcon=1 \
        ad=8.8e-14 as=8.8e-14 pd=1.42u ps=1.42u nrd=1.5652 nrs=1.5652 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends amk_inverter
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_nand
// View name: schematic
subckt amk_nand VDD VSS a b z
    T1 (z b VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T3 (z a VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T2 (net17 b VSS VSS) lpnfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T0 (z a net17 VSS) lpnfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends amk_nand
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: dac_latch
// View name: schematic
subckt dac_latch D Q VDD VSS clk
    I4 (VDD VSS D net7) amk_inverter
    I3 (VDD VSS Q net22 net15) amk_nand
    I2 (VDD VSS net27 net15 Q) amk_nand
    I1 (VDD VSS clk net7 net22) amk_nand
    I0 (VDD VSS D clk net27) amk_nand
ends dac_latch
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: simple_switch
// View name: schematic
subckt simple_switch VDD VSS cntrl in out
    T0 (out cntrl in VSS) lpnfet l=120.0n w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.18 nrs=0.18 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    I0 (VDD VSS cntrl net8) amk_inverter
    T1 (out net8 in VDD) lppfet l=120.0n w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.18 nrs=0.18 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends simple_switch
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_mux
// View name: schematic
subckt amk_mux VDD VSS in out sel
    I3 (VDD VSS sel net021) amk_inverter
    I2 (VDD VSS sel in out) simple_switch
    T0 (in net021 VSS VSS) lpnfet l=120.0n w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.18 nrs=0.18 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends amk_mux
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: current_scaler_res
// View name: schematic
subckt current_scaler_res VDD VSS Vref clock in0 in1 in2 in3 in4 in5 in6 \
        in7 in8 in9 out
    R9 (net150 net0202) resistor r=0
    R15 (out net068) resistor r=0
    R11 (net138 net0192) resistor r=0
    R7 (net180 net0227) resistor r=0
    R8 (net0162 net0182) resistor r=0
    R10 (net144 net0197) resistor r=0
    R12 (net132 net0187) resistor r=0
    R6 (net174 net0222) resistor r=0
    R5 (net168 net0217) resistor r=0
    R4 (net162 net0212) resistor r=0
    R3 (net156 net0207) resistor r=0
    I55 (in7 in7_out VDD VSS clock) dac_latch
    I56 (in8 in8_out VDD VSS clock) dac_latch
    I49 (in5 in5_out VDD VSS clock) dac_latch
    I57 (in9 in9_out VDD VSS clock) dac_latch
    I54 (in0 in0_out VDD VSS clock) dac_latch
    I53 (in1 in1_out VDD VSS clock) dac_latch
    I52 (in2 in2_out VDD VSS clock) dac_latch
    I63 (in3 in3_out VDD VSS clock) dac_latch
    I50 (in4 in4_out VDD VSS clock) dac_latch
    I47 (in6 in6_out VDD VSS clock) dac_latch
    nwres20 (net71 VSS VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=300 \
        dtemp=0 rsx=50 sh=1
    nwres19 (net74 net71 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 \
        sbar=150 dtemp=0 rsx=50 sh=1
    nwres18 (net77 net74 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 \
        sbar=150 dtemp=0 rsx=50 sh=1
    nwres17 (net80 net77 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 \
        sbar=150 dtemp=0 rsx=50 sh=1
    nwres16 (net83 net80 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 \
        sbar=150 dtemp=0 rsx=50 sh=1
    nwres15 (net86 net83 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 \
        sbar=150 dtemp=0 rsx=50 sh=1
    nwres14 (net89 net86 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 \
        sbar=150 dtemp=0 rsx=50 sh=1
    nwres13 (net92 net89 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 \
        sbar=150 dtemp=0 rsx=50 sh=1
    nwres12 (net122 net92 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 \
        sbar=150 dtemp=0 rsx=50 sh=1
    nwres11 (net71 net132 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 \
        sbar=300 dtemp=0 rsx=50 sh=1
    nwres10 (net74 net138 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 \
        sbar=300 dtemp=0 rsx=50 sh=1
    nwres9 (net77 net144 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 \
        sbar=300 dtemp=0 rsx=50 sh=1
    nwres8 (net80 net150 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 \
        sbar=300 dtemp=0 rsx=50 sh=1
    nwres7 (net83 net156 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 \
        sbar=300 dtemp=0 rsx=50 sh=1
    nwres6 (net86 net162 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 \
        sbar=300 dtemp=0 rsx=50 sh=1
    nwres5 (net89 net168 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 \
        sbar=300 dtemp=0 rsx=50 sh=1
    nwres4 (net92 net174 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 \
        sbar=300 dtemp=0 rsx=50 sh=1
    nwres2 (net068 net122 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 \
        sbar=150 dtemp=0 rsx=50 sh=1
    nwres3 (net122 net180 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 \
        sbar=300 dtemp=0 rsx=50 sh=1
    nwres0 (net068 net0162 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 \
        sbar=300 dtemp=0 rsx=50 sh=1
    I9 (VDD VSS net0187 Vref in0_out) amk_mux
    I8 (VDD VSS net0192 Vref in1_out) amk_mux
    I7 (VDD VSS net0197 Vref in2_out) amk_mux
    I6 (VDD VSS net0202 Vref in3_out) amk_mux
    I5 (VDD VSS net0207 Vref in4_out) amk_mux
    I4 (VDD VSS net0212 Vref in5_out) amk_mux
    I3 (VDD VSS net0217 Vref in6_out) amk_mux
    I2 (VDD VSS net0222 Vref in7_out) amk_mux
    I1 (VDD VSS net0227 Vref in8_out) amk_mux
    I10 (VDD VSS net0182 Vref in9_out) amk_mux
ends current_scaler_res
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_buf
// View name: schematic
subckt amk_buf VDD VSS bout in
    I1 (VDD VSS net10 bout) amk_inverter
    I0 (VDD VSS in net10) amk_inverter
ends amk_buf
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: buf_string
// View name: schematic
subckt buf_string VDD VSS in out
    I14 (VDD VSS out net10) amk_buf
    I13 (VDD VSS net10 net14) amk_buf
    I12 (VDD VSS net14 net18) amk_buf
    I11 (VDD VSS net18 net22) amk_buf
    I10 (VDD VSS net22 net42) amk_buf
    I9 (VDD VSS net26 net46) amk_buf
    I8 (VDD VSS net30 net26) amk_buf
    I7 (VDD VSS net34 net30) amk_buf
    I6 (VDD VSS net38 net34) amk_buf
    I5 (VDD VSS net42 net38) amk_buf
    I4 (VDD VSS net46 net50) amk_buf
    I3 (VDD VSS net50 net54) amk_buf
    I2 (VDD VSS net54 net58) amk_buf
    I1 (VDD VSS net58 net62) amk_buf
    I0 (VDD VSS net62 in) amk_buf
ends buf_string
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_nand_3in
// View name: schematic
subckt amk_nand_3in VDD VSS a b c z
    T4 (net10 c VSS VSS) lpnfet l=120.0n w=440.0n nf=1 m=1 par=1 ngcon=1 \
        ad=2.42e-13 as=2.42e-13 pd=1.98u ps=1.98u nrd=0.4091 nrs=0.4091 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T0 (z a net18 VSS) lpnfet l=120.0n w=440.0n nf=1 m=1 par=1 ngcon=1 \
        ad=2.42e-13 as=2.42e-13 pd=1.98u ps=1.98u nrd=0.4091 nrs=0.4091 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T2 (net18 b net10 VSS) lpnfet l=120.0n w=440.0n nf=1 m=1 par=1 ngcon=1 \
        ad=2.42e-13 as=2.42e-13 pd=1.98u ps=1.98u nrd=0.4091 nrs=0.4091 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T5 (z c VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T3 (z a VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T1 (z b VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends amk_nand_3in
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_latch_qb
// View name: schematic
subckt amk_latch_qb D Q QB VDD VSS clk clr
    I5 (VDD VSS Q net066 clr QB) amk_nand_3in
    I3 (VDD VSS clk net28 clr net066) amk_nand_3in
    I0 (VDD VSS D clk net9) amk_nand
    I2 (VDD VSS net9 QB Q) amk_nand
    I4 (VDD VSS D net28) amk_inverter
ends amk_latch_qb
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_dff_qb
// View name: schematic
subckt amk_dff_qb D Q QB VDD VSS clk clr
    I4 (D net9 net024 VDD VSS net19 net038) amk_latch_qb
    I1 (net9 Q QB VDD VSS clk net038) amk_latch_qb
    I6 (VDD clk clr net038) amk_inverter
    I2 (VDD VSS clk net19) amk_inverter
ends amk_dff_qb
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_3in_and
// View name: schematic
subckt amk_3in_and VDD VSS a b c z
    I0 (VDD VSS net17 z) amk_inverter
    T5 (net17 c VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T3 (net17 a VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T1 (net17 b VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T4 (net048 c VSS VSS) lpnfet l=120.0n w=480.0n nf=1 m=1 par=1 ngcon=1 \
        ad=2.64e-13 as=2.64e-13 pd=2.06u ps=2.06u nrd=0.375 nrs=0.375 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T2 (net21 b net048 VSS) lpnfet l=120.0n w=480.0n nf=1 m=1 par=1 \
        ngcon=1 ad=2.64e-13 as=2.64e-13 pd=2.06u ps=2.06u nrd=0.375 \
        nrs=0.375 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 \
        lstis=1 lnws=0 rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p \
        panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p \
        sa=5.5e-07 sb=5.5e-07 sd=0u dtemp=0
    T0 (net17 a net21 VSS) lpnfet l=120.0n w=480.0n nf=1 m=1 par=1 ngcon=1 \
        ad=2.64e-13 as=2.64e-13 pd=2.06u ps=2.06u nrd=0.375 nrs=0.375 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends amk_3in_and
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_2in_and
// View name: schematic
subckt amk_2in_and VDD VSS a b z
    T0 (net17 a net13 VSS) lpnfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T2 (net13 b VSS VSS) lpnfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T3 (net17 a VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T1 (net17 b VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    I0 (VDD VSS net17 z) amk_inverter
ends amk_2in_and
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_dff_fe
// View name: schematic
subckt amk_dff_fe D Q VDD VSS clk rst
    I7 (D net028 net030 VDD VSS clk rstb) amk_latch_qb
    I8 (net028 Q net020 VDD VSS net7 rstb) amk_latch_qb
    I9 (VDD VSS rst rstb) amk_inverter
    I2 (VDD VSS clk net7) amk_inverter
ends amk_dff_fe
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_2in_or
// View name: schematic
subckt amk_2in_or VDD VSS a b z
    I0 (VDD VSS net21 z) amk_inverter
    T1 (net12 a VDD VDD) lppfet l=120.0n w=480.0n nf=1 m=1 par=1 ngcon=1 \
        ad=2.64e-13 as=2.64e-13 pd=2.06u ps=2.06u nrd=0.375 nrs=0.375 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T3 (net21 b net12 VDD) lppfet l=120.0n w=480.0n nf=1 m=1 par=1 ngcon=1 \
        ad=2.64e-13 as=2.64e-13 pd=2.06u ps=2.06u nrd=0.375 nrs=0.375 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T2 (net21 a VSS VSS) lpnfet l=120.0n w=160.0n nf=1 m=1 par=1 ngcon=1 \
        ad=8.8e-14 as=8.8e-14 pd=1.42u ps=1.42u nrd=1.125 nrs=1.125 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T0 (net21 b VSS VSS) lpnfet l=120.0n w=160.0n nf=1 m=1 par=1 ngcon=1 \
        ad=8.8e-14 as=8.8e-14 pd=1.42u ps=1.42u nrd=1.125 nrs=1.125 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends amk_2in_or
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: sar_mux
// View name: schematic
subckt sar_mux VDD VSS in0 in1 out sel0
    I1 (VDD VSS net54 net49 out) amk_2in_or
    I0 (VDD VSS sel0 sel0b) amk_inverter
    I9 (VDD VSS in1 sel0 net49) amk_2in_and
    I6 (VDD VSS in0 sel0b net54) amk_2in_and
ends sar_mux
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: SAR_logic2
// View name: schematic
subckt SAR_logic2 VDD VSS bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 \
        bit9 c0 c1 c2 c3 clock compOut done reset toDAC0 toDAC1 toDAC2 \
        toDAC3 toDAC4 toDAC5 toDAC6 toDAC7 toDAC8 toDAC9
    I126 (VDD VSS clock clk) buf_string
    I63 (VDD beginProc net0168 VDD VSS clk9 reset) amk_dff_qb
    I10 (VDD VSS c3 c3b) amk_inverter
    I9 (VDD VSS c2 c2b) amk_inverter
    I8 (VDD VSS c1 c1b) amk_inverter
    I7 (VDD VSS c0 c0b) amk_inverter
    I42 (VDD VSS c2_0 c2_1 clk clk2) amk_3in_and
    I52 (VDD VSS c0_0 c0_1 clk clk0) amk_3in_and
    I47 (VDD VSS c1_0 c1_1 clk clk1) amk_3in_and
    I37 (VDD VSS c3_0 c3_1 clk clk3) amk_3in_and
    I32 (VDD VSS c4_0 c4_1 clk clk4) amk_3in_and
    I17 (VDD VSS c7_0 c7_1 clk clk7) amk_3in_and
    I12 (VDD VSS c8_0 c8_1 clk clk8) amk_3in_and
    I6 (VDD VSS c9_0 c9_1 clk clk9) amk_3in_and
    I27 (VDD VSS c5_0 c5_1 clk clk5) amk_3in_and
    I22 (VDD VSS c6_0 c6_1 clk clk6) amk_3in_and
    I68 (VDD VSS clk7 beginProc net0263) amk_2in_and
    I67 (VDD VSS clk8 beginProc net0268) amk_2in_and
    I74 (VDD VSS clk1 beginProc net0264) amk_2in_and
    I75 (VDD VSS clk0 beginProc net0259) amk_2in_and
    I69 (VDD VSS clk6 beginProc net0203) amk_2in_and
    I71 (VDD VSS clk4 beginProc net0279) amk_2in_and
    I72 (VDD VSS clk3 beginProc net0274) amk_2in_and
    I73 (VDD VSS clk2 beginProc net0269) amk_2in_and
    I54 (VDD VSS c2b c3 c0_1) amk_2in_and
    I53 (VDD VSS c0 c1b c0_0) amk_2in_and
    I43 (VDD VSS c0 c1 c2_0) amk_2in_and
    I44 (VDD VSS c2 c3b c2_1) amk_2in_and
    I70 (VDD VSS clk5 beginProc net0199) amk_2in_and
    I48 (VDD VSS c2b c3 c1_1) amk_2in_and
    I49 (VDD VSS c0b c1b c1_0) amk_2in_and
    I39 (VDD VSS c0b c1 c3_0) amk_2in_and
    I38 (VDD VSS c2 c3b c3_1) amk_2in_and
    I34 (VDD VSS c2 c3b c4_1) amk_2in_and
    I33 (VDD VSS c0 c1b c4_0) amk_2in_and
    I29 (VDD VSS c0b c1b c5_0) amk_2in_and
    I28 (VDD VSS c2 c3b c5_1) amk_2in_and
    I19 (VDD VSS c0b c1 c7_0) amk_2in_and
    I18 (VDD VSS c2b c3b c7_1) amk_2in_and
    I14 (VDD VSS c2b c3b c8_1) amk_2in_and
    I13 (VDD VSS c0 c1b c8_0) amk_2in_and
    I66 (VDD VSS clk9 beginProc net0215) amk_2in_and
    I65 (VDD VSS c2b c3b c9_1) amk_2in_and
    I3 (VDD VSS c0b c1b c9_0) amk_2in_and
    I23 (VDD VSS c0 c1 c6_0) amk_2in_and
    I24 (VDD VSS c2b c3b c6_1) amk_2in_and
    I45 (net0310 bit2 VDD VSS net0269 reset) amk_dff_fe
    I55 (net0371 bit0 VDD VSS net0259 reset) amk_dff_fe
    I57 (VDD done VDD VSS net0259 reset) amk_dff_fe
    I50 (net0377 bit1 VDD VSS net0264 reset) amk_dff_fe
    I40 (net180 bit3 VDD VSS net0274 reset) amk_dff_fe
    I35 (net186 bit4 VDD VSS net0279 reset) amk_dff_fe
    I30 (net192 bit5 VDD VSS net0199 reset) amk_dff_fe
    I20 (net204 bit7 VDD VSS net0263 reset) amk_dff_fe
    I15 (net210 bit8 VDD VSS net0268 reset) amk_dff_fe
    I2 (net216 bit9 VDD VSS net0215 reset) amk_dff_fe
    I25 (net198 bit6 VDD VSS net0203 reset) amk_dff_fe
    I81 (VDD VSS bit8 VDD toDAC8 clk8) sar_mux
    I85 (VDD VSS bit7 VDD toDAC7 clk7) sar_mux
    I89 (VDD VSS bit6 VDD toDAC6 clk6) sar_mux
    I101 (VDD VSS bit3 VDD toDAC3 clk3) sar_mux
    I109 (VDD VSS bit1 VDD toDAC1 clk1) sar_mux
    I56 (VDD VSS VSS VDD net0371 compOut) sar_mux
    I46 (VDD VSS VSS VDD net0310 compOut) sar_mux
    I97 (VDD VSS bit4 VDD toDAC4 clk4) sar_mux
    I113 (VDD VSS bit0 VDD toDAC0 clk0) sar_mux
    I105 (VDD VSS bit2 VDD toDAC2 clk2) sar_mux
    I76 (VDD VSS bit9 VDD toDAC9 clk9) sar_mux
    I51 (VDD VSS VSS VDD net0377 compOut) sar_mux
    I41 (VDD VSS VSS VDD net180 compOut) sar_mux
    I36 (VDD VSS VSS VDD net186 compOut) sar_mux
    I31 (VDD VSS VSS VDD net192 compOut) sar_mux
    I21 (VDD VSS VSS VDD net204 compOut) sar_mux
    I16 (VDD VSS VSS VDD net210 compOut) sar_mux
    I11 (VDD VSS VSS VDD net216 compOut) sar_mux
    I93 (VDD VSS bit5 VDD toDAC5 clk5) sar_mux
    I26 (VDD VSS VSS VDD net198 compOut) sar_mux
ends SAR_logic2
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: nmos_amp
// View name: schematic
subckt nmos_amp VDD VSS out ref vin\+ vin\-
    T4 (VDD net10 net10 VDD) lppfet l=5u w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.22 nrs=0.22 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T5 (out net10 VDD VDD) lppfet l=5u w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.22 nrs=0.22 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T0 (VSS ref net057 VSS) lpnfet l=15.0u w=240.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.32e-13 as=1.32e-13 pd=1.58u ps=1.58u nrd=0.9167 nrs=0.9167 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T1 (net10 vin\+ net057 VSS) lpnfet l=5u w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.22 nrs=0.22 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T7 (net057 vin\- out VSS) lpnfet l=5u w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.22 nrs=0.22 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends nmos_amp
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: pmos_amp
// View name: schematic
subckt pmos_amp VDD VSS out ref vin\+ vin\-
    T1 (VSS net5 net5 VSS) lpnfet l=10u w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.22 nrs=0.22 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T7 (out net5 VSS VSS) lpnfet l=10u w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.22 nrs=0.22 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T0 (net036 ref VDD VDD) lppfet l=10u w=200n nf=1 m=1 par=1 ngcon=1 \
        ad=1.1e-13 as=1.1e-13 pd=1.5u ps=1.5u nrd=1.1 nrs=1.1 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T4 (net5 vin\+ net036 VDD) lppfet l=5u w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.22 nrs=0.22 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T5 (net036 vin\- out VDD) lppfet l=5u w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.22 nrs=0.22 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends pmos_amp
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: comparator1
// View name: schematic
subckt comparator1 VDD VSS in\+ in\- out vref
    I8 (VDD VSS net043 net41) amk_buf
    I9 (VDD VSS net039 net31) amk_buf
    I7 (VDD VSS amp1o net078) amk_buf
    I10 (VDD VSS out net15) amk_buf
    T2 (net039 net22 net15 VDD) lppfet l=1u w=20u nf=1 m=1 par=1 ngcon=1 \
        ad=1.1e-11 as=1.1e-11 pd=41.1u ps=41.1u nrd=0.011 nrs=0.011 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T1 (net043 amp1o net15 VDD) lppfet l=1u w=20u nf=1 m=1 par=1 ngcon=1 \
        ad=1.1e-11 as=1.1e-11 pd=41.1u ps=41.1u nrd=0.011 nrs=0.011 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T3 (net039 amp1o net15 VSS) lpnfet l=1u w=10u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-12 as=5.5e-12 pd=21.1u ps=21.1u nrd=0.022 nrs=0.022 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T0 (net043 net22 net15 VSS) lpnfet l=1u w=10u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-12 as=5.5e-12 pd=21.1u ps=21.1u nrd=0.022 nrs=0.022 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    I6 (VDD VSS amp1o net22) amk_inverter
    I2 (VDD VSS net31 vref in\+ in\-) nmos_amp
    I1 (VDD VSS net41 vref in\+ in\-) pmos_amp
    I0 (VDD VSS net078 vref in\+ in\-) pmos_amp
ends comparator1
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: an_switch
// View name: schematic
subckt an_switch VDD VSS cntrl in0 in1 sel_out
    I0 (VDD VSS cntrl cntrlb) amk_inverter
    T2 (sel_out cntrlb in0 VSS) lpnfet l=120.0n w=160.0n nf=1 m=1 par=1 \
        ngcon=1 ad=8.8e-14 as=8.8e-14 pd=1.42u ps=1.42u nrd=1.5652 \
        nrs=1.5652 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 \
        lstis=1 lnws=0 rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p \
        panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p \
        sa=5.5e-07 sb=5.5e-07 sd=0u dtemp=0
    T1 (sel_out cntrl in1 VSS) lpnfet l=120.0n w=160.0n nf=1 m=1 par=1 \
        ngcon=1 ad=8.8e-14 as=8.8e-14 pd=1.42u ps=1.42u nrd=1.5652 \
        nrs=1.5652 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 \
        lstis=1 lnws=0 rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p \
        panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p \
        sa=5.5e-07 sb=5.5e-07 sd=0u dtemp=0
    T3 (sel_out cntrl in0 VDD) lppfet l=120.0n w=160.0n nf=1 m=1 par=1 \
        ngcon=1 ad=8.8e-14 as=8.8e-14 pd=1.42u ps=1.42u nrd=1.5652 \
        nrs=1.5652 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 \
        lstis=1 lnws=0 rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p \
        panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p \
        sa=5.5e-07 sb=5.5e-07 sd=0u dtemp=0
    T0 (sel_out cntrlb in1 VDD) lppfet l=120.0n w=160.0n nf=1 m=1 par=1 \
        ngcon=1 ad=8.8e-14 as=8.8e-14 pd=1.42u ps=1.42u nrd=1.5652 \
        nrs=1.5652 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 \
        lstis=1 lnws=0 rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p \
        panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p \
        sa=5.5e-07 sb=5.5e-07 sd=0u dtemp=0
ends an_switch
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: cap_dac
// View name: schematic
subckt cap_dac VDD VSS comp_in Vref in0 in1 in2 in3 in4 in5 in6 in7 in8 \
        in9 reset
    V0 (comp_in net042) vsource dc=0 type=dc
    V1 (comp_in net0140) vsource dc=0 type=dc
    V2 (comp_in net0143) vsource dc=0 type=dc
    V3 (comp_in net0146) vsource dc=0 type=dc
    V4 (comp_in net0149) vsource dc=0 type=dc
    V5 (comp_in net052) vsource dc=0 type=dc
    V6 (comp_in net0158) vsource dc=0 type=dc
    V7 (comp_in net056) vsource dc=0 type=dc
    V8 (comp_in net058) vsource dc=0 type=dc
    V9 (comp_in net0152) vsource dc=0 type=dc
    I34 (VDD VSS reset VSS comp_in) simple_switch
    I28 (VDD VSS in5 VSS Vref net52) an_switch
    I32 (VDD VSS in1 VSS Vref net32) an_switch
    I30 (VDD VSS in3 VSS Vref net42) an_switch
    I29 (VDD VSS in4 VSS Vref net47) an_switch
    I31 (VDD VSS in2 VSS Vref net37) an_switch
    I33 (VDD VSS in0 VSS Vref net27) an_switch
    I26 (VDD VSS in7 VSS Vref net62) an_switch
    I27 (VDD VSS in6 VSS Vref net57) an_switch
    I25 (VDD VSS in8 VSS Vref net67) an_switch
    I24 (VDD VSS in9 VSS Vref net72) an_switch
    CM12 (VSS comp_in VSS) mimcap l=8.5u w=5.24u c=95.62136f m=1 par=1 \
        est=1 tlev1=3 tlev2=2 bp=3 setind=-2 rsx=50 dtemp=0
    CM9 (net27 net042 VSS) mimcap l=8.5u w=5.24u c=95.62136f m=1 par=1 \
        est=1 tlev1=3 tlev2=2 bp=3 setind=-2 rsx=50 dtemp=0
    CM8 (net32 net0140 VSS) mimcap l=8.5u w=10.63u c=191.2346f m=1 par=1 \
        est=1 tlev1=3 tlev2=2 bp=3 setind=-2 rsx=50 dtemp=0
    CM7 (net37 net0143 VSS) mimcap l=8.5u w=21.41u c=382.461f m=1 par=1 \
        est=1 tlev1=3 tlev2=2 bp=3 setind=-2 rsx=50 dtemp=0
    CM6 (net42 net0146 VSS) mimcap l=8.5u w=42.97u c=764.9138f m=1 par=1 \
        est=1 tlev1=3 tlev2=2 bp=3 setind=-2 rsx=50 dtemp=0
    CM5 (net47 net0149 VSS) mimcap l=8.5u w=86.04u c=1.528933p m=1 par=1 \
        est=1 tlev1=3 tlev2=2 bp=3 setind=-2 rsx=50 dtemp=0
    CM4 (net72 net0152 VSS) mimcap l=8.5u w=2.75976m c=48.95805p m=1 par=1 \
        est=1 tlev1=3 tlev2=2 bp=3 setind=-2 rsx=50 dtemp=0
    CM3 (net52 net052 VSS) mimcap l=8.5u w=172.29u c=3.058921p m=1 par=1 \
        est=1 tlev1=3 tlev2=2 bp=3 setind=-2 rsx=50 dtemp=0
    CM2 (net57 net0158 VSS) mimcap l=8.5u w=344.8u c=6.119076p m=1 par=1 \
        est=1 tlev1=3 tlev2=2 bp=3 setind=-2 rsx=50 dtemp=0
    CM1 (net62 net056 VSS) mimcap l=8.5u w=689.8u c=12.23903p m=1 par=1 \
        est=1 tlev1=3 tlev2=2 bp=3 setind=-2 rsx=50 dtemp=0
    CM0 (net67 net058 VSS) mimcap l=8.5u w=1.3798m c=24.47894p m=1 par=1 \
        est=1 tlev1=3 tlev2=2 bp=3 setind=-2 rsx=50 dtemp=0
ends cap_dac
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_tff
// View name: schematic
subckt amk_tff Q QB T VDD VSS clear clk
    I5 (net20 Q QB VDD VSS clk clear) amk_dff_qb
    I4 (VDD VSS T net15) amk_inverter
    I3 (VDD VSS net25 net30 net20) amk_2in_or
    I2 (VDD VSS Q net15 net25) amk_2in_and
    I1 (VDD VSS T QB net30) amk_2in_and
ends amk_tff
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: up_counter
// View name: schematic
subckt up_counter Q0 Q1 Q2 Q3 VDD VSS clear clk en
    I6 (en net033 net035 VDD VSS clk clear) amk_dff_qb
    I4 (Q3 net10 VDD VDD VSS clear net16) amk_tff
    I3 (Q2 net16 VDD VDD VSS clear net22) amk_tff
    I2 (Q1 net22 VDD VDD VSS clear net28) amk_tff
    I1 (Q0 net28 net033 VDD VSS clear clk) amk_tff
ends up_counter
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: sar_adc2
// View name: schematic
subckt sar_adc2 VDD VSS Vref an_in b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 clk \
        compRef done start
    I14 (VDD VSS b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 count0 count1 count2 count3 \
        outb compOut done startb din0 din1 din2 din3 din4 din5 din6 din7 \
        din8 din9) SAR_logic2
    I11_1 (out im_1 noconn_1 VDD VSS net092 clk_clr_1) amk_dff_qb
    I11_2 (im_1 im_2 noconn_2 VDD VSS net092 clk_clr_2) amk_dff_qb
    I11_3 (im_2 im_3 noconn_3 VDD VSS net092 clk_clr_3) amk_dff_qb
    I11_4 (im_3 im_4 noconn_4 VDD VSS net092 clk_clr_4) amk_dff_qb
    I11_5 (im_4 im_5 noconn_5 VDD VSS net092 clk_clr_5) amk_dff_qb
    I11_6 (im_5 im_6 noconn_6 VDD VSS net092 clk_clr_6) amk_dff_qb
    I11_7 (im_6 im_7 noconn_7 VDD VSS net092 clk_clr_7) amk_dff_qb
    I11_8 (im_7 im_8 noconn_8 VDD VSS net092 clk_clr_8) amk_dff_qb
    I11_9 (im_8 im_9 noconn_9 VDD VSS net092 clk_clr_9) amk_dff_qb
    I11_10 (im_9 im_10 noconn_10 VDD VSS net092 clk_clr_10) amk_dff_qb
    I3 (VDD VSS an_in net89 compOut compRef) comparator1
    I16 (VDD VSS clk net092) amk_inverter
    I17 (VDD VSS im_10 out) amk_inverter
    I18 (VDD VSS out outb) amk_inverter
    I12_1 (VDD VSS start clk_clr_1) amk_inverter
    I12_2 (VDD VSS start clk_clr_2) amk_inverter
    I12_3 (VDD VSS start clk_clr_3) amk_inverter
    I12_4 (VDD VSS start clk_clr_4) amk_inverter
    I12_5 (VDD VSS start clk_clr_5) amk_inverter
    I12_6 (VDD VSS start clk_clr_6) amk_inverter
    I12_7 (VDD VSS start clk_clr_7) amk_inverter
    I12_8 (VDD VSS start clk_clr_8) amk_inverter
    I12_9 (VDD VSS start clk_clr_9) amk_inverter
    I12_10 (VDD VSS start clk_clr_10) amk_inverter
    I2 (VDD VSS start startb) amk_inverter
    I57 (VDD VSS net89 Vref din0 din1 din2 din3 din4 din5 din6 din7 din8 \
        din9 startb) cap_dac
    I60 (count0 count1 count2 count3 VDD VSS startb outb start) up_counter
ends sar_adc2
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: ADC_and_DAC
// View name: schematic
T0 (headerV done VDD VDD) lppfet l=120.0n w=8u nf=1 m=1 par=1 ngcon=1 \
        ad=4.4e-12 as=4.4e-12 pd=17.1u ps=17.1u nrd=0.0225 nrs=0.0225 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
V0 (net7 VSS) vsource dc=500.0m type=dc
I1 (VDD VSS VDD done net38 net37 net36 net35 net34 net33 net32 net31 net30 \
        net29 out_v) current_scaler_res
I0 (headerV VSS VDD an_in net38 net37 net36 net35 net34 net33 net32 net31 \
        net30 net29 clk net7 done start) sar_adc2
